国语熟妇乱人伦A片久久,同桌把他的J坐进我的下面,苏苏的放荡日记高H无删减全,AV天堂午夜精品一区

Design & Verification

Home Products Digital Design EDA

NavisPro

Hierarchical SoC Design Planning Solution

RTL Design Planning Hierarchical Floorplanning Global Channel Planning

NavisPro provides an RTL SoC design planning solution that predicts and prevents the design issues commonly found in the physical implementation stage. 

  • Constraints-driven RTL design floorplanning for better QoR

  • Addresses complexity problem of SoC design via intelligent partitioning of the full chip into many blocks or sub-systems

  • Chip partitioning includes physical hierarchical partitions of the design and pin placement of each sub-system

  • Accurate estimation of the bus interconnect timing between sub-systems


Download Brochure

Highlights

  • Mixed Levels

    Mixed-level design planning (RTL/Gate/Black-box)

  • Flexibility

    Flexible design abstraction management

  • Rich Features

    Rich sets of key engineering features

  • Automation

    Automatic block pin assignment &
    bus interconnect planning

  • Ease of Use

    Efficient RTL design planning with minimum efforts for input data preparation

  • Efficiency

    Reducing design TAT
    by minimization of design iterations

Applications

  • Large & complex
    SoC design

  • Design & constraints exploration

  • Constraints-driven floorplanning

  • Automatic/manual
    pin assignment

  • Routing congestion estimation

  • BUS interconnect planning

  • Hierarchical floorplanning

Contact TOP

Log in

泰宁县| 吉林市| 将乐县| 长葛市| 忻州市| 宜兴市| 西充县| 清苑县| 万载县| 宁德市| 上蔡县| 合山市|